2010
Designing CMOS circuits for low power Book
Springer Publishing Company, Incorporated, 2010.
2008
Performance for Cryptography: hardware and software approach Book Chapter
In: pp. 403-418, 2008, ISBN: 978-1-60456-186-9.
2004
A Novel Constant-Time Fault-Secure Binary Counter Proceedings Article
In: Macii, Enrico; Paliouras, Vassilis; Koufopavlou, Odysseas (Ed.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, pp. 742–749, Springer Berlin Heidelberg, Berlin, Heidelberg, 2004, ISBN: 978-3-540-30205-6.
2003
A novel high-speed counter with counting rate independent of the counter's length Proceedings Article
In: 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, pp. 1164-1167 Vol.3, 2003.
A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits Journal Article
In: Journal of Circuits, Systems and Computers, vol. 12, no. 01, pp. 75-91, 2003.
2002
A Fast Johnson-Mobius Encoding Scheme for Fault Secure Binary Counters Proceedings Article
In: 2002.
Designing CMOS circuits for low power Book
Springer Publishing Company, Incorporated, 2010.
Performance for Cryptography: hardware and software approach Book Chapter
In: pp. 403-418, 2008, ISBN: 978-1-60456-186-9.
A Novel Constant-Time Fault-Secure Binary Counter Proceedings Article
In: Macii, Enrico; Paliouras, Vassilis; Koufopavlou, Odysseas (Ed.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, pp. 742–749, Springer Berlin Heidelberg, Berlin, Heidelberg, 2004, ISBN: 978-3-540-30205-6.
A novel high-speed counter with counting rate independent of the counter's length Proceedings Article
In: 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, pp. 1164-1167 Vol.3, 2003.
A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits Journal Article
In: Journal of Circuits, Systems and Computers, vol. 12, no. 01, pp. 75-91, 2003.
A Fast Johnson-Mobius Encoding Scheme for Fault Secure Binary Counters Proceedings Article
In: 2002.
A low power fault secure timer implementation based on the Gray encoding scheme Proceedings Article
In: 9th International Conference on Electronics, Circuits and Systems, pp. 537-540 vol.2, 2002.
A Comparative Study on Fault Secure Signed Multiplication Designs Proceedings Article
In: 2001.
The Effect of Fault Secureness in Low Power Multiplier Designs Proceedings Article
In: 2001.
Hardware/Power Requirements vs. Fault Detection Effectiveness in Self-Checking Circuits Proceedings Article
In: PATMOS'99. Proceedings of PATMOS '99. IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation, pp. 387-396, 1999.
Hardware and Power Requirements of Self-Checking Circuits Proceedings Article
In: ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), pp. 1655-1658, 1999.