2019
A High-Performance Neuron for Artificial Neural Network based on Izhikevich model Proceedings Article
In: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 29–34, IEEE 2019.
2017
Systolic Binary Counter using a Cellular Automaton-based Prescaler Proceedings Article
In: Proceedings of the 21st Pan-Hellenic Conference on Informatics, pp. 1–4, 2017.
2015
A compact design of SEED block cipher Proceedings Article
In: 2015 4th Mediterranean Conference on Embedded Computing (MECO), pp. 119-123, 2015.
2011
Exploration and enhancement of P1619-based crypto-cores for efficient performance Proceedings Article
In: 2011 IEEE International Conference on Consumer Electronics (ICCE), pp. 361-362, 2011.
2010
Implementation of a P1619 crypto-core for Shared Storage Media Proceedings Article
In: Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference, pp. 597-601, 2010.
2007
Implementation of HSSec: a High–Speed Cryptographic Co-Processor Proceedings Article
In: 2007 IEEE Conference on Emerging Technologies and Factory Automation (EFTA 2007), pp. 625-631, 2007.
A High-Performance Neuron for Artificial Neural Network based on Izhikevich model Proceedings Article
In: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 29–34, IEEE 2019.
Systolic Binary Counter using a Cellular Automaton-based Prescaler Proceedings Article
In: Proceedings of the 21st Pan-Hellenic Conference on Informatics, pp. 1–4, 2017.
A compact design of SEED block cipher Proceedings Article
In: 2015 4th Mediterranean Conference on Embedded Computing (MECO), pp. 119-123, 2015.
Exploration and enhancement of P1619-based crypto-cores for efficient performance Proceedings Article
In: 2011 IEEE International Conference on Consumer Electronics (ICCE), pp. 361-362, 2011.
Implementation of a P1619 crypto-core for Shared Storage Media Proceedings Article
In: Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference, pp. 597-601, 2010.
Implementation of HSSec: a High–Speed Cryptographic Co-Processor Proceedings Article
In: 2007 IEEE Conference on Emerging Technologies and Factory Automation (EFTA 2007), pp. 625-631, 2007.
High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications Journal Article
In: The Journal of Supercomputing, vol. 37, pp. 179-195, 2006.
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems Journal Article
In: Microelectronics Journal, vol. 37, no. 6, pp. 554-564, 2006, ISSN: 0026-2692.
Speedups from partitioning software kernels to FPGA hardware in embedded SoCs Proceedings Article
In: IEEE Workshop on Signal Processing Systems Design and Implementation, 2005., pp. 485-490, 2005.
A high-throughput area efficient FPGA implementation of AES-128 Encryption Proceedings Article
In: IEEE Workshop on Signal Processing Systems Design and Implementation, 2005., pp. 116-121, 2005.
Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function Proceedings Article
In: Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004., pp. 567-570, 2004.
