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2019

Sapounaki, Maria; Kakarountas, Athanasios

A High-Performance Neuron for Artificial Neural Network based on Izhikevich model Proceedings Article

In: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 29–34, IEEE 2019.

BibTeX | Tags: Digital Circuits, FPGA, Hardware Accelerator

2017

Chioktour, Vasileios; Spathoulas, Georgios; Kakarountas, Athanasios

Systolic Binary Counter using a Cellular Automaton-based Prescaler Proceedings Article

In: Proceedings of the 21st Pan-Hellenic Conference on Informatics, pp. 1–4, 2017.

BibTeX | Tags: Digital Circuits, FPGA, Hardware Accelerator

2015

Pirpilidis, F; Kitsos, P; Kakarountas, A

A compact design of SEED block cipher Proceedings Article

In: 2015 4th Mediterranean Conference on Embedded Computing (MECO), pp. 119-123, 2015.

Links | BibTeX | Tags: FPGA, Hardware Accelerator

2011

Hatzidimitriou, E; Kakarountas, A P; Milidonis, A

Exploration and enhancement of P1619-based crypto-cores for efficient performance Proceedings Article

In: 2011 IEEE International Conference on Consumer Electronics (ICCE), pp. 361-362, 2011.

Links | BibTeX | Tags: Computer Architecture, FPGA, Hardware Accelerator, security

2010

Hatzidimitriou, E; Kakarountas, A P

Implementation of a P1619 crypto-core for Shared Storage Media Proceedings Article

In: Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference, pp. 597-601, 2010.

Links | BibTeX | Tags: Computer Architecture, Embedded Systems, FPGA, security

2007

Kakarountas, A P; Michail, H; Goutis, C E; Efstathiou, C

Implementation of HSSec: a High–Speed Cryptographic Co-Processor Proceedings Article

In: 2007 IEEE Conference on Emerging Technologies and Factory Automation (EFTA 2007), pp. 625-631, 2007.

Links | BibTeX | Tags: Computer Architecture, FPGA, Hardware Accelerator, security

11 entries « 1 of 2 »

Show all

1.

Sapounaki, Maria; Kakarountas, Athanasios

A High-Performance Neuron for Artificial Neural Network based on Izhikevich model Proceedings Article

In: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 29–34, IEEE 2019.

BibTeX

2.

Chioktour, Vasileios; Spathoulas, Georgios; Kakarountas, Athanasios

Systolic Binary Counter using a Cellular Automaton-based Prescaler Proceedings Article

In: Proceedings of the 21st Pan-Hellenic Conference on Informatics, pp. 1–4, 2017.

BibTeX

3.

Pirpilidis, F; Kitsos, P; Kakarountas, A

A compact design of SEED block cipher Proceedings Article

In: 2015 4th Mediterranean Conference on Embedded Computing (MECO), pp. 119-123, 2015.

Links | BibTeX

4.

Hatzidimitriou, E; Kakarountas, A P; Milidonis, A

Exploration and enhancement of P1619-based crypto-cores for efficient performance Proceedings Article

In: 2011 IEEE International Conference on Consumer Electronics (ICCE), pp. 361-362, 2011.

Links | BibTeX

5.

Hatzidimitriou, E; Kakarountas, A P

Implementation of a P1619 crypto-core for Shared Storage Media Proceedings Article

In: Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference, pp. 597-601, 2010.

Links | BibTeX

6.

Kakarountas, A P; Michail, H; Goutis, C E; Efstathiou, C

Implementation of HSSec: a High–Speed Cryptographic Co-Processor Proceedings Article

In: 2007 IEEE Conference on Emerging Technologies and Factory Automation (EFTA 2007), pp. 625-631, 2007.

Links | BibTeX

7.

Kakarountas, Athanasios; Michail, Harris; Milidonis, Athanasios; Goutis, Costas; Theodoridis, George

High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications Journal Article

In: The Journal of Supercomputing, vol. 37, pp. 179-195, 2006.

Links | BibTeX

8.

Galanis, Michalis D; Milidonis, Athanassios; Kakarountas, Athanassios P; Goutis, Costas E

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems Journal Article

In: Microelectronics Journal, vol. 37, no. 6, pp. 554-564, 2006, ISSN: 0026-2692.

Abstract | Links | BibTeX

9.

Galanis, M D; Dimitroulakos, G; Kakarountas, A P; Goutis, C E

Speedups from partitioning software kernels to FPGA hardware in embedded SoCs Proceedings Article

In: IEEE Workshop on Signal Processing Systems Design and Implementation, 2005., pp. 485-490, 2005.

Links | BibTeX

10.

Brokalakis, A; Kakarountas, A P; Goutis, C E

A high-throughput area efficient FPGA implementation of AES-128 Encryption Proceedings Article

In: IEEE Workshop on Signal Processing Systems Design and Implementation, 2005., pp. 116-121, 2005.

Links | BibTeX

11.

Michail, H E; Kakarountas, A P; Milidonis, A; Goutis, C E

Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function Proceedings Article

In: Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004., pp. 567-570, 2004.

BibTeX